A bipolar transistor, which is formed through silicon selective epitaxial growth and operates as a fast operation bipolar transistor, is disclosed in JP-A 79394/1998. (the term “JP-A” as used herein designates an “unexamined published Japanese patent application”). Hereinafter, an example will be described which is referred to as conventional example 1. FIG. 2 shows a cross sectional view of a bipolar transistor constituting the conventional example 1. In FIG. 2, reference numerals and symbols are defined as follows; 101 denotes a silicon substrate, 102 denotes a high concentration n-type buried layer, 103 denotes a low concentration n-type buried layer (single crystal silicon), 104 denotes a trench isolation, 105 denotes a collector-base isolation film, 106 denotes an extrinsic base electrode, each of 107, 107a, 113, and 116 denotes an emitter-base isolation film, 108 denotes a low concentration n-type buried layer (single crystal silicon germanium), 109 denotes a p-type intrinsic base layer (single crystal silicon germanium), 110 denotes a p-type extrinsic base layer (polycrystalline silicon germanium), 111 denotes a low concentration cap layer (single crystal silicon or single crystal silicon germanium), 112 denotes a low concentration polycrystalline silicon (or low concentration polycrystalline silicon germanium), 114 denotes an emitter electrode, 115 denotes an emitter region, 116 denotes an insulator, 117 denotes a high concentration n-type collector contact layer, and 118 denotes an electrode.
In the conventional example 1, n-type impurity ions are diffused thermally from the emitter electrode 114 into the low concentration cap layer 111 to form the emitter region 115. And, the p-type extrinsic base layer 110 formed together with the p-type intrinsic base layer 109 is used for the junction between the p-type intrinsic base layer 109 and the extrinsic base electrode 106.
Another bipolar transistor, which will be described hereinafter as conventional example 2, is disclosed in JP-A 92837/1998. FIG. 3 shows a cross sectional view of the bipolar transistor constituting the conventional example 2. In FIG. 3, reference numerals and symbols are defined as follows; 201 denotes a first N-type silicon layer, 202 denotes a first silicon oxide film, 203 denotes a polycrystalline silicon layer, 204 denotes a second silicon oxide film, 205 denotes a silicon nitride film, 206 denotes an emitter opening, each of 207 and 212 denotes a sidewall, 208 denotes a second N-type silicon layer, 209 denotes an N-type polycrystalline silicon layer, 210 denotes a silicon germanium base layer, 211 denotes a third N-type silicon layer, 213 denotes an N+ polycrystalline silicon layer, and 214 denotes a third silicon oxide layer.
In the conventional example 2, the silicon germanium base layer 210 and the polycrystalline silicon layer 203 that functions as an extrinsic base are connected to each other by the N-type polycrystalline silicon layer 209 formed together with the second N-type silicon layer through thermal diffusion of P-type impurity ions from the polycrystalline silicon layer 203. The third N-type silicon layer that functions as an emitter is selectively formed on the silicon germanium base layer 210 so as to be surrounded by the sidewall 207 after the base layer 210 is formed so as to reach the bottom of the sidewall 207.
To improve the performance of a bipolar transistor, a high cutoff frequency, a low base resistance, and a low base-collector capacitance are required. To raise the cutoff frequency, the base layer film is required to be thin. However, if the base layer film is thin, the base resistance increases and the breakdown voltage goes low. To avoid such problems, it is necessary to raise the concentration of the base layer. If the concentration of the base layer is raised, the concentration of the emitter is lowered with respect to the concentration of the base layer, thereby the current gain of the transistor tends to go down. Recently, to cope with such problems, hetero-bipolar transistors have been used, because they can exhibit an increased current gain by providing a heterojunction between the emitter and the base. The bipolar transistor in the conventional example 1 is structured as a hetero bipolar transistor of this kind. On the other hand, the base-collector capacitance tends to increase due to the employment of high concentration collector layers to speed up the operation of those transistors. Consequently, the junction area is now required to be reduced such as by use of a self-aligned process.
In the bipolar transistor in the conventional example 1, as shown in FIG. 2, the emitter-base isolation film 107a and the film 113 may be thinned and the distance between the intrinsic region and the extrinsic base electrode 106 may be reduced to lower the base resistance. In this structure, the extrinsic base layer 110 is formed so as to extend toward the emitter of the extrinsic base electrode 106 only by the amount of the film thickness from the side end of the emitter. And, if the low concentration cap layer 111 is formed, the low concentration polycrystalline silicon 112 is formed so as to extend toward the emitter by the amount of the film thickness. In addition, because thermal diffusion occurs from the emitter electrode 114 to the low concentration cap film 111 to form the emitter region 115, the emitter region and its periphery are expanded by the depth of the region from the intrinsic region to the extrinsic base. As a result, if the distance between the intrinsic region and the extrinsic base electrode becomes shorter than the sum of the film thickness of the extrinsic base layer, the film thickness of the low concentration cap layer, and the depth of the emitter region, the emitter is formed in the region of the low concentration polycrystalline silicon 112. Therefore, the base current leakage tends to increase due to the recombination. For this reason, to obtain favorable electrical characteristics that are capable of reducing the leakage current with this structure, the distance between the intrinsic region and the extrinsic base electrode had to be wider than the above-described sum. Even when transistors are to be miniaturized more to reduce the base-collector capacitance, a certain distance between the intrinsic region and the extrinsic base electrode is required around the intrinsic region. It has thus been difficult to reduce the components related to the capacitance.
There is another method that may be employed for reducing the base resistance. The method calls for lowering the resistance of the extrinsic base layer 110 for connecting the base layer to the extrinsic base electrode 106. To do this, it is proposed that the concentration of the extrinsic base layer 110 should be raised and the extrinsic base region should be expanded. To raise the concentration of the extrinsic base layer, a method is proposed that raises the temperature or increases the time of the thermal treatment for the extrinsic base layer 110, thereby to accelerate the diffusion of impurity more from the extrinsic base electrode. This method, for the sake of its objective, suffers from a re-distribution of the impurity profile of the intrinsic region, resulting in an impediment to the speedup of the transistor operation. There is another method that increases the contact area between the base layer and the extrinsic base electrode so as to lower the base resistance. This also suffers from an increase in the base-connector junction area, causing the base-collector capacitance to increase.
In FIG. 3 (the conventional example 2), the periphery of the emitter layer 211 is covered by the sidewall 207. The base layer other than the intrinsic base can be reduced in length by thinning the film of this sidewall 207, which is a method of preventing the base current from leaking. However, in this method, for the sake of the manufacturing process, the base layer 210 becomes thinner than the intrinsic region at the bottom of the sidewall 207, causing the sheet resistance of the base layer to increase at that thinner portion. In addition, the method is also structured such that, if the base layer 210 is formed only inside the sidewall 207, impurity ions are diffused from the polycrystalline silicon 203 under a thermal treatment to form a junction between the base layer 210 and the polycrystalline silicon layer 203. However, because a p-type layer is formed deeply in the lower portion of the polycrystalline silicon layer 203, the base-collector capacitance increases and the base layer becomes thick due to heat diffusion. Thinning the base layer to speed up the operation has thus been limited by itself.
As described above, it has been difficult to satisfy the requirements for achieving a high cutoff frequency, a low base resistance, and a low base-collector capacitance at the same time in the conventional structures, using standard manufacturing methods, of semiconductor devices.